Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
Ingelsson, Urban ; Goel, Sandeep Kumar ; Larsson, Erik LU
and Marinissen, Erik Jan
(2005)
IEEE European Test Symposium ETS 05, 2005
p.8-13
- Abstract
- Complex SOCs areincreasingly tested in a modular fashion, which enables us torecord the yield-per-module. In this paper, we consider theyield-per-module as the pass probability of the module smanufacturing test. We use it to exploit the abort-on-fail featureof ATEs, in order to reduce the expected test application time. Wepresent a model for expected test application time, which obtainsincreasing accuracy due to decreasing granularity of the abortabletest unit. For a given SOC, with a modular test architectureconsisting of wrappers and disjunct TAMs, and for given passprobabilities per module test, we schedule the tests on each TAMsuch that the expected test application time is minimized. Wedescribe two heuristic scheduling approaches, one... (More)
- Complex SOCs areincreasingly tested in a modular fashion, which enables us torecord the yield-per-module. In this paper, we consider theyield-per-module as the pass probability of the module smanufacturing test. We use it to exploit the abort-on-fail featureof ATEs, in order to reduce the expected test application time. Wepresent a model for expected test application time, which obtainsincreasing accuracy due to decreasing granularity of the abortabletest unit. For a given SOC, with a modular test architectureconsisting of wrappers and disjunct TAMs, and for given passprobabilities per module test, we schedule the tests on each TAMsuch that the expected test application time is minimized. Wedescribe two heuristic scheduling approaches, one without and onewith preemption. Experimental results for the ITC 02 SOC TestBenchmarks demonstrate the effectiveness of our approach, as weachieve up to 97% reduction in the expected test application time,without any modification to the SOC or ATE. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341081
- author
- Ingelsson, Urban
; Goel, Sandeep Kumar
; Larsson, Erik
LU
and Marinissen, Erik Jan
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, systems-on-chip, yield-per-module, TAM, test scheduling
- host publication
- [Host publication title missing]
- pages
- 8 - 13
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE European Test Symposium ETS 05, 2005
- conference location
- Tallinn, Estonia
- conference dates
- 2005-05-22 - 2005-05-25
- external identifiers
-
- scopus:33744485048
- ISBN
- 0-7695-2341-2
- DOI
- 10.1109/ETS.2005.38
- language
- English
- LU publication?
- no
- id
- 07243a4c-b351-423c-bd8f-1bd5bba27779 (old id 2341081)
- date added to LUP
- 2016-04-04 11:02:59
- date last changed
- 2022-02-06 06:43:10
@inproceedings{07243a4c-b351-423c-bd8f-1bd5bba27779,
abstract = {{Complex SOCs areincreasingly tested in a modular fashion, which enables us torecord the yield-per-module. In this paper, we consider theyield-per-module as the pass probability of the module smanufacturing test. We use it to exploit the abort-on-fail featureof ATEs, in order to reduce the expected test application time. Wepresent a model for expected test application time, which obtainsincreasing accuracy due to decreasing granularity of the abortabletest unit. For a given SOC, with a modular test architectureconsisting of wrappers and disjunct TAMs, and for given passprobabilities per module test, we schedule the tests on each TAMsuch that the expected test application time is minimized. Wedescribe two heuristic scheduling approaches, one without and onewith preemption. Experimental results for the ITC 02 SOC TestBenchmarks demonstrate the effectiveness of our approach, as weachieve up to 97% reduction in the expected test application time,without any modification to the SOC or ATE.}},
author = {{Ingelsson, Urban and Goel, Sandeep Kumar and Larsson, Erik and Marinissen, Erik Jan}},
booktitle = {{[Host publication title missing]}},
isbn = {{0-7695-2341-2}},
keywords = {{testing; systems-on-chip; yield-per-module; TAM; test scheduling}},
language = {{eng}},
pages = {{8--13}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Test Scheduling for Modular SOCs in an Abort-on-Fail Environment}},
url = {{http://dx.doi.org/10.1109/ETS.2005.38}},
doi = {{10.1109/ETS.2005.38}},
year = {{2005}},
}