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A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration

Lu, Ping LU ; Wu, Ying and Andreani, Piero LU (2016) In IEEE Transactions on Circuits and Systems - II - Express Briefs p.1019-1023
Abstract
This paper presents a 2-dimension (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65nm CMOS process and consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the average latency time (within 2ns) is less... (More)
This paper presents a 2-dimension (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65nm CMOS process and consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the average latency time (within 2ns) is less than 1/6 of that in a standard Vernier TDC. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
ime to digital converter (TDC), Gated-Ring-Oscillator (GRO), Vernier, 2-dimension (2-D)
in
IEEE Transactions on Circuits and Systems - II - Express Briefs
pages
5 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:84994476949
  • wos:000387900900003
ISSN
1549-7747
DOI
10.1109/TCSII.2016.2548218
language
English
LU publication?
yes
id
08645fa9-2566-42c6-9eb0-9587e037ccf5
date added to LUP
2016-05-03 16:39:40
date last changed
2017-01-01 08:24:32
@article{08645fa9-2566-42c6-9eb0-9587e037ccf5,
  abstract     = {This paper presents a 2-dimension (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65nm CMOS process and consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the average latency time (within 2ns) is less than 1/6 of that in a standard Vernier TDC.},
  author       = {Lu, Ping and Wu, Ying and Andreani, Piero},
  issn         = {1549-7747},
  keyword      = {ime  to  digital  converter  (TDC),Gated-Ring-Oscillator (GRO),Vernier, 2-dimension  (2-D)},
  language     = {eng},
  month        = {03},
  pages        = {1019--1023},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems - II - Express Briefs},
  title        = {A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration},
  url          = {http://dx.doi.org/10.1109/TCSII.2016.2548218},
  year         = {2016},
}