Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations

Andersson, Mattias LU ; Andersson, Martin LU ; Sundström, Lars LU and Andreani, Pietro LU (2012) IEEE Asian Solid-State Circuits Conference (ASSCC), 2012 p.245-248
Abstract
This paper presents a 3rd-order, 3-bit continuous time (CT) Delta-Sigma modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65nm CMOS process, where it occupies an area of 0.2mmx0.4mm. It achieves an SNR of 71dB and an SNDR of 69dB over a 9MHz bandwidth with an oversampling ratio of 16. Power consumption is 7.5mW from a 1.2V supply, for a figure-of-merit of 181fJ/conversion.
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
IEEE Asian Solid State Circuits Conference (A-SSCC), 2012
pages
245 - 248
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Asian Solid-State Circuits Conference (ASSCC), 2012
conference location
Kobe, Japan
conference dates
2012-11-12 - 2012-11-14
external identifiers
  • scopus:84881073465
ISBN
978-1-4673-2468-8
DOI
10.1109/IPEC.2012.6522671
project
EIT_DRAGON Digital Radio Architectures Going Nanoscale
language
English
LU publication?
yes
id
0dfc2cd0-ebc7-4b79-baf6-3a48cb7673d9 (old id 3218102)
date added to LUP
2016-04-04 11:37:45
date last changed
2022-01-29 22:09:33
@inproceedings{0dfc2cd0-ebc7-4b79-baf6-3a48cb7673d9,
  abstract     = {{This paper presents a 3rd-order, 3-bit continuous time (CT) Delta-Sigma modulator for an LTE radio receiver. By adopting a return-to-zero (RZ) pulse in the innermost DAC, the modulator shows a reduced sensitivity to loop-delay variations, and the additional loop delay compensation usually needed in CT modulators can be omitted. The modulator has been implemented in a 65nm CMOS process, where it occupies an area of 0.2mmx0.4mm. It achieves an SNR of 71dB and an SNDR of 69dB over a 9MHz bandwidth with an oversampling ratio of 16. Power consumption is 7.5mW from a 1.2V supply, for a figure-of-merit of 181fJ/conversion.}},
  author       = {{Andersson, Mattias and Andersson, Martin and Sundström, Lars and Andreani, Pietro}},
  booktitle    = {{IEEE Asian Solid State Circuits Conference (A-SSCC), 2012}},
  isbn         = {{978-1-4673-2468-8}},
  language     = {{eng}},
  pages        = {{245--248}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations}},
  url          = {{http://dx.doi.org/10.1109/IPEC.2012.6522671}},
  doi          = {{10.1109/IPEC.2012.6522671}},
  year         = {{2012}},
}