Advanced

A fully Integrated Standard-Cell Digital PLL

Olsson, Thomas LU and Nilsson, Peter LU (2001) In Electronics Letters 37(4). p.211-212
Abstract
A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Electronics Letters
volume
37
issue
4
pages
211 - 212
publisher
IEE
external identifiers
  • scopus:6644224989
ISSN
1350-911X
DOI
10.1049/el:20010160
language
English
LU publication?
yes
id
b3dade1e-fe9c-4e06-854c-8c77bcb9b9a6 (old id 1033970)
date added to LUP
2008-02-22 13:23:43
date last changed
2017-01-01 07:52:37
@article{b3dade1e-fe9c-4e06-854c-8c77bcb9b9a6,
  abstract     = {A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2},
  author       = {Olsson, Thomas and Nilsson, Peter},
  issn         = {1350-911X},
  language     = {eng},
  number       = {4},
  pages        = {211--212},
  publisher    = {IEE},
  series       = {Electronics Letters},
  title        = {A fully Integrated Standard-Cell Digital PLL},
  url          = {http://dx.doi.org/10.1049/el:20010160},
  volume       = {37},
  year         = {2001},
}