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Wordlength Optimization of a Pipelined FFT Processor

Johansson, Stefan; He, Shousheng LU and Nilsson, Peter LU (1999) 1999 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’99) In 42nd Midwest Symposium on Circuits and Systems, 1999. 1. p.501-503
Abstract
This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance on be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses large memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are... (More)
This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance on be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses large memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are therefore used to find an acceptable solution. The simulations show that a good solution is obtained by starting with 12 bits and gradually increasing the wordlength up to 16 bits. The final result is rounded back to 12 bits. This is a good trade-off between precision and complexity (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
42nd Midwest Symposium on Circuits and Systems, 1999.
volume
1
pages
501 - 503
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
1999 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’99)
external identifiers
  • Scopus:0033292513
ISBN
0-7803-5491-5
DOI
10.1109/MWSCAS.1999.867314
language
English
LU publication?
yes
id
8dc9dfc8-f4cc-45da-9d3d-9b0d207da9c3 (old id 1034082)
date added to LUP
2008-02-27 09:22:28
date last changed
2017-01-01 07:59:04
@inproceedings{8dc9dfc8-f4cc-45da-9d3d-9b0d207da9c3,
  abstract     = {This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance on be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses large memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are therefore used to find an acceptable solution. The simulations show that a good solution is obtained by starting with 12 bits and gradually increasing the wordlength up to 16 bits. The final result is rounded back to 12 bits. This is a good trade-off between precision and complexity},
  author       = {Johansson, Stefan and He, Shousheng and Nilsson, Peter},
  booktitle    = {42nd Midwest Symposium on Circuits and Systems, 1999.},
  isbn         = {0-7803-5491-5},
  language     = {eng},
  pages        = {501--503},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Wordlength Optimization of a Pipelined FFT Processor},
  url          = {http://dx.doi.org/10.1109/MWSCAS.1999.867314},
  volume       = {1},
  year         = {1999},
}