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A 8-bit 100-MHz CMOS linear interpolation DAC

Yijun, Zhou LU and Yuan, Jiren LU (2003) In IEEE Journal of Solid-State Circuits 38(10). p.1758-1761
Abstract
An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The... (More)
An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Journal of Solid-State Circuits
volume
38
issue
10
pages
1758 - 1761
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000185568500024
  • scopus:0141885993
ISSN
0018-9200
DOI
10.1109/JSSC.2003.817593
language
English
LU publication?
yes
id
1930ce03-eec9-48c9-82ba-5daa70dc73cf (old id 1049669)
date added to LUP
2008-03-20 11:35:05
date last changed
2017-10-01 04:54:14
@article{1930ce03-eec9-48c9-82ba-5daa70dc73cf,
  abstract     = {An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.},
  author       = {Yijun, Zhou and Yuan, Jiren},
  issn         = {0018-9200},
  language     = {eng},
  number       = {10},
  pages        = {1758--1761},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {A 8-bit 100-MHz CMOS linear interpolation DAC},
  url          = {http://dx.doi.org/10.1109/JSSC.2003.817593},
  volume       = {38},
  year         = {2003},
}