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New single clock CMOS latches and flipflops with improved speed and power savings

Yuan, Jiren LU and Svensson, Christer (1997) In IEEE Journal of Solid-State Circuits 32(1). p.62-69
Abstract
New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type... (More)
New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Journal of Solid-State Circuits
volume
32
issue
1
pages
62 - 69
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:0030828211
ISSN
0018-9200
DOI
10.1109/4.553179
language
English
LU publication?
yes
id
19c8cbc6-af38-467c-b9d3-9b005e404467 (old id 1049670)
date added to LUP
2008-03-20 11:37:09
date last changed
2017-08-13 04:25:42
@article{19c8cbc6-af38-467c-b9d3-9b005e404467,
  abstract     = {New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.},
  author       = {Yuan, Jiren and Svensson, Christer},
  issn         = {0018-9200},
  language     = {eng},
  number       = {1},
  pages        = {62--69},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {New single clock CMOS latches and flipflops with improved speed and power savings},
  url          = {http://dx.doi.org/10.1109/4.553179},
  volume       = {32},
  year         = {1997},
}