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A 0.2V 0.44 uW 20 kHz Analog to Digital Sigma-Delta Modulator with 57 fJ/conversion FoM

Wismar, Ulrik; Wisland, Dag and Andreani, Pietro LU (2006) In Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006. p.187-190
Abstract
This paper presents a 90 nm CMOS A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 muW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.
pages
187 - 190
external identifiers
  • Scopus:44849118533
ISSN
1930-8833
ISBN
1-4244-0303-0
DOI
10.1109/ESSCIR.2006.307562
language
English
LU publication?
no
id
adff92f7-99d7-425f-a450-82345132deb2 (old id 1051077)
alternative location
http://ieeexplore.ieee.org/iel5/4099684/4099685/04099735.pdf?tp=&isnumber=4099685&arnumber=4099735&punumber=4099684
date added to LUP
2008-03-31 12:02:21
date last changed
2017-02-19 04:27:20
@inproceedings{adff92f7-99d7-425f-a450-82345132deb2,
  abstract     = {This paper presents a 90 nm CMOS A/D modulator operating with a supply voltage of 0.2 V, well below the threshold voltage of the transistors. The modulator is an open-loop first-order architecture based on a frequency-modulated intermediate signal, generated in a ring voltage-controlled oscillator. The linearity of the modulator is greatly improved by the adoption of a so-called soft-rail in the oscillator. Measurements show a dynamic range of 52 dB over a 20 kHz signal bandwidth with a sampling frequency of 3.4 MHz, for a total power consumption as low as 0.44 muW. The corresponding peak SNDR is 44.2 dB, while the peak SNR is 47.4 dB},
  author       = {Wismar, Ulrik and Wisland, Dag and Andreani, Pietro},
  booktitle    = {Proceedings of the 32nd European Solid-State Circuits Conference, 2006. ESSCIRC 2006.},
  isbn         = {1-4244-0303-0},
  issn         = {1930-8833},
  language     = {eng},
  pages        = {187--190},
  title        = {A 0.2V 0.44 uW 20 kHz Analog to Digital Sigma-Delta Modulator with 57 fJ/conversion FoM},
  url          = {http://dx.doi.org/10.1109/ESSCIR.2006.307562},
  year         = {2006},
}