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Arithmetic reduction of adder leakage in nanoscale CMOS

Nilsson, Peter LU (2008) The 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008) In 2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 p.717-720
Abstract
in today’s technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4
pages
717 - 720
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
The 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2008)
external identifiers
  • WOS:000268007100179
  • Scopus:62949148862
ISBN
978-1-4244-2341-5
language
English
LU publication?
yes
id
11e7ba40-c6f8-4c35-8baa-9f82cabf9935 (old id 1212783)
date added to LUP
2008-08-12 13:59:26
date last changed
2017-01-01 07:55:35
@inproceedings{11e7ba40-c6f8-4c35-8baa-9f82cabf9935,
  abstract     = {in today’s technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.},
  author       = {Nilsson, Peter},
  booktitle    = {2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4},
  isbn         = {978-1-4244-2341-5},
  language     = {eng},
  pages        = {717--720},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Arithmetic reduction of adder leakage in nanoscale CMOS},
  year         = {2008},
}