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Constraint-driven identification of application specific instructions in the DURASE system

Martin, Kevin; Wolinski, Christophe; Kuchcinski, Krzysztof LU ; Floch, Antoine and Charot, Francois (2009) SAMOS IX: International Workshop on Systems, Architectures, Modeling and Simulation In Embedded Computer Systems: Architectures, Modeling, and Simulation / Lecture notes in computer science 5657. p.194-203
Abstract
This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of <em>DURASE</em> system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor extension generation. Our method identifies all computational patterns directly from an application graph satisfying all architectural and technological constraints imposed by target processors and FPGA devices. The considered constraints include a number of inputs and outputs, a number of operators, and a delay of the pattern critical path. Therefore the identified... (More)
This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of <em>DURASE</em> system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor extension generation. Our method identifies all computational patterns directly from an application graph satisfying all architectural and technological constraints imposed by target processors and FPGA devices. The considered constraints include a number of inputs and outputs, a number of operators, and a delay of the pattern critical path. Therefore the identified patterns can be well tailored to target processors. Our approach uses heavily constraint programming methods, which makes it possible to mix graph isomorphism constraints with other constraints in one formal environment. We have extensively evaluated our algorithm on MediaBench and MiBench benchmarks with tough architectural and technological constraints. The obtained patterns have good coverage of application graphs while limiting number of operators and fulfill architectural and technological constraints. (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
Embedded Computer Systems: Architectures, Modeling, and Simulation / Lecture notes in computer science
volume
5657
pages
194 - 203
publisher
Springer
conference name
SAMOS IX: International Workshop on Systems, Architectures, Modeling and Simulation
external identifiers
  • scopus:70350416669
ISSN
1611-3349
0302-9743
ISBN
978-3-642-03137-3
DOI
10.1007/978-3-642-03138-0_21
project
EASE
language
English
LU publication?
yes
id
2b100a59-b57c-4a39-9d80-5d8e859824f1 (old id 1368823)
date added to LUP
2009-04-06 10:58:11
date last changed
2017-09-10 03:51:36
@inproceedings{2b100a59-b57c-4a39-9d80-5d8e859824f1,
  abstract     = {This paper presents a new constraint-driven method for fast identification of computational patterns that is a part of &lt;em&gt;DURASE&lt;/em&gt; system (Generic Environment for Design and Utilization of Reconfigurable Application-Specific Processors Extensions). The patterns identified by our system form a base for application specific instruction selection and processor extension generation. Our method identifies all computational patterns directly from an application graph satisfying all architectural and technological constraints imposed by target processors and FPGA devices. The considered constraints include a number of inputs and outputs, a number of operators, and a delay of the pattern critical path. Therefore the identified patterns can be well tailored to target processors. Our approach uses heavily constraint programming methods, which makes it possible to mix graph isomorphism constraints with other constraints in one formal environment. We have extensively evaluated our algorithm on MediaBench and MiBench benchmarks with tough architectural and technological constraints. The obtained patterns have good coverage of application graphs while limiting number of operators and fulfill architectural and technological constraints.},
  author       = {Martin, Kevin and Wolinski, Christophe and Kuchcinski, Krzysztof and Floch, Antoine and Charot, Francois},
  booktitle    = {Embedded Computer Systems: Architectures, Modeling, and Simulation / Lecture notes in computer science},
  isbn         = {978-3-642-03137-3},
  issn         = {1611-3349},
  language     = {eng},
  pages        = {194--203},
  publisher    = {Springer},
  title        = {Constraint-driven identification of application specific instructions in the DURASE system},
  url          = {http://dx.doi.org/10.1007/978-3-642-03138-0_21},
  volume       = {5657},
  year         = {2009},
}