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Reduction of substrate noise in sub clock frequency range

Sherazi, Syed Muhammad Yasser LU ; Asif, Shahzad; Backenius, Erik and Vesterbacka, Mark (2010) In IEEE Transactions on Circuits and Systems Part 1: Regular Papers 57(6). p.1287-1297
Abstract
We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130 nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The... (More)
We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130 nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where a 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption. (Less)
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organization
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publication status
published
subject
keywords
Reduction of Substrate Noise in Sub Clock Frequency Range, 120nm
in
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
volume
57
issue
6
pages
1287 - 1297
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000281783800017
  • scopus:77953477061
ISSN
1549-8328
DOI
10.1109/TCSI.2009.2031749
language
English
LU publication?
yes
id
0419f3cf-187b-4ed9-8df5-7db596f8d374 (old id 1451599)
date added to LUP
2010-02-11 12:43:40
date last changed
2018-05-29 12:19:59
@article{0419f3cf-187b-4ed9-8df5-7db596f8d374,
  abstract     = {We propose a method of reducing the switching noise in the substrate of an integrated circuit. The main idea is to design the digital circuits to obtain a periodic supply current with the same period as the clock. This property locates the frequency components of the switching noise above the clock frequency. Differential return-to-zero signaling is used to reduce the data-dependency of the current. Circuits are implemented in symmetrical precharged DCVS logic with internally asynchronous D registers. A chip was fabricated in a standard 130 nm CMOS technology holding two versions of a pipelined 16-bit adder. First version employed the proposed method, and second version used conventional static CMOS logic circuits and TSPC registers. The respective device counts are 1190 and 684, and maximal operating frequencies 450 and 375 MHz. Frequency domain measurements were performed at the substrate node with on-chip generated sinusoidal and pseudo-random data at a clock frequency of 300 MHz. The sinusoidal case resulted in the largest frequency components, where a 8.5 dB/Hz decrease in maximal power is measured for the proposed circuitry at a cost of three times larger power consumption.},
  author       = {Sherazi, Syed Muhammad Yasser and Asif, Shahzad and Backenius, Erik and Vesterbacka, Mark},
  issn         = {1549-8328},
  keyword      = {Reduction of Substrate Noise in Sub Clock Frequency Range,120nm},
  language     = {eng},
  number       = {6},
  pages        = {1287--1297},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems Part 1: Regular Papers},
  title        = {Reduction of substrate noise in sub clock frequency range},
  url          = {http://dx.doi.org/10.1109/TCSI.2009.2031749},
  volume       = {57},
  year         = {2010},
}