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Architectures and arithmetic for low static power consumption in nanoscale CMOS

Nilsson, Peter LU (2009) In VLSI Design
Abstract
This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length, i.e. the gain in power ratio is larger for longer word lengths. A static power ratio at... (More)
This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length, i.e. the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
VLSI Design
issue
Article ID 749272
publisher
Hindawi Publishing Corporation
external identifiers
  • scopus:76649094950
ISSN
1065-514X
DOI
10.1155/2009/749272
language
English
LU publication?
yes
id
d23cb934-04c2-4d30-8a71-cfc78bb3797f (old id 1487673)
date added to LUP
2009-10-19 12:37:54
date last changed
2017-01-01 07:33:51
@article{d23cb934-04c2-4d30-8a71-cfc78bb3797f,
  abstract     = {This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length, i.e. the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.},
  author       = {Nilsson, Peter},
  issn         = {1065-514X},
  language     = {eng},
  number       = {Article ID 749272},
  publisher    = {Hindawi Publishing Corporation},
  series       = {VLSI Design},
  title        = {Architectures and arithmetic for low static power consumption in nanoscale CMOS},
  url          = {http://dx.doi.org/10.1155/2009/749272},
  year         = {2009},
}