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Implementation of an SVD Based MIMO OFDM channel estimator

Löfgren, Johan LU ; Mehmood, Shahid ; Khan, Nadir ; Masood, Babar ; Awan, M. Irfan Z. ; Khan, Imran ; Chisty, Nafiz A. and Nilsson, Peter LU (2010) Norchip Conference, 2009
Abstract
This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these... (More)
This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented. (Less)
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author
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organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2009 NORCHIP
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
Norchip Conference, 2009
conference location
Trondheim, Norway
conference dates
2009-11-16 - 2009-11-17
external identifiers
  • scopus:77949633365
ISBN
978-1-4244-4311-6
9781424443109
DOI
10.1109/NORCHP.2009.5397840
language
English
LU publication?
yes
id
b13cca2e-62f8-4b89-b4b8-8d6623db7443 (old id 1487674)
date added to LUP
2016-04-04 11:10:56
date last changed
2025-01-06 18:01:54
@inproceedings{b13cca2e-62f8-4b89-b4b8-8d6623db7443,
  abstract     = {{This paper presents a hardware design of an SVD based channel estimator. The details of the design are explained and some key aspects are discussed. The design has been implemented and tested on an FPGA and synthesized for an ASIC in 130 nm technology. It is shown that it is possible to get a clock frequency of 179 MHz for a 1.38 mm 2 design. This corresponds to ~30 M estimates per second, which is more than needed in current wireless systems. Further, simulations show that this design would consume an average power of around 8.5 mW with a peak power at 14.2 mW. The presented data shows that it is possible to use these kind of advanced channel estimation strategies in wireless receivers, even though there has been no prior reports of these being implemented.}},
  author       = {{Löfgren, Johan and Mehmood, Shahid and Khan, Nadir and Masood, Babar and Awan, M. Irfan Z. and Khan, Imran and Chisty, Nafiz A. and Nilsson, Peter}},
  booktitle    = {{2009 NORCHIP}},
  isbn         = {{978-1-4244-4311-6}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Implementation of an SVD Based MIMO OFDM channel estimator}},
  url          = {{http://dx.doi.org/10.1109/NORCHP.2009.5397840}},
  doi          = {{10.1109/NORCHP.2009.5397840}},
  year         = {{2010}},
}