Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices
Cavo, Luis ; Fuhrmann, Sébastien and Liu, Liang LU
(2020)
In Microprocessors and Microsystems
72.
- Abstract
Providing information security is crucial for the Internet of Things (IoT) devices, platforms in which the available power budget is very limited. This paper tackles this challenge and presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) NarrowBand IoT (NB-IoT) standard. The proposed processor has been optimized to the needs of the low end portfolio technologies that compose the IoT market, which addresses low-area, low-cost and low-data rate applications. Operation analysis at the algorithm-level and hardware sharing at the architecture-level have enabled extensive area reduction. The cryptographic processor has been described... (More)
Providing information security is crucial for the Internet of Things (IoT) devices, platforms in which the available power budget is very limited. This paper tackles this challenge and presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) NarrowBand IoT (NB-IoT) standard. The proposed processor has been optimized to the needs of the low end portfolio technologies that compose the IoT market, which addresses low-area, low-cost and low-data rate applications. Operation analysis at the algorithm-level and hardware sharing at the architecture-level have enabled extensive area reduction. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a general purpose processor in a cycle accurate virtual platform. The design achieves a reduction of area ranging from 5% to 42% in comparison to similar work. Synthesis results using a 65-nm CMOS technology show that the processor has a hardware cost of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.
(Less)
- author
- Cavo, Luis
; Fuhrmann, Sébastien
and Liu, Liang
LU
- organization
- publishing date
- 2020
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- 3G, AES, confidentiality, cryptography, high level synthesis, integrated circuits, integrity, low power, NB-IoT, processor, Snow, Zuc
- in
- Microprocessors and Microsystems
- volume
- 72
- article number
- 102899
- publisher
- Elsevier
- external identifiers
-
- scopus:85074158108
- ISSN
- 0141-9331
- DOI
- 10.1016/j.micpro.2019.102899
- language
- English
- LU publication?
- yes
- id
- 15e7ae75-7b00-453b-8582-444f3451daf0
- date added to LUP
- 2019-11-05 10:35:36
- date last changed
- 2024-04-02 18:24:42
@article{15e7ae75-7b00-453b-8582-444f3451daf0,
abstract = {{<p>Providing information security is crucial for the Internet of Things (IoT) devices, platforms in which the available power budget is very limited. This paper tackles this challenge and presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) NarrowBand IoT (NB-IoT) standard. The proposed processor has been optimized to the needs of the low end portfolio technologies that compose the IoT market, which addresses low-area, low-cost and low-data rate applications. Operation analysis at the algorithm-level and hardware sharing at the architecture-level have enabled extensive area reduction. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a general purpose processor in a cycle accurate virtual platform. The design achieves a reduction of area ranging from 5% to 42% in comparison to similar work. Synthesis results using a 65-nm CMOS technology show that the processor has a hardware cost of 53.6 kGE, and is capable of performing at 52.4 Mbps for the block cipher and 800 Mbps for the stream cipher algorithms at a 100 MHz clock.</p>}},
author = {{Cavo, Luis and Fuhrmann, Sébastien and Liu, Liang}},
issn = {{0141-9331}},
keywords = {{3G; AES; confidentiality; cryptography; high level synthesis; integrated circuits; integrity; low power; NB-IoT; processor; Snow; Zuc}},
language = {{eng}},
publisher = {{Elsevier}},
series = {{Microprocessors and Microsystems}},
title = {{Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices}},
url = {{http://dx.doi.org/10.1016/j.micpro.2019.102899}},
doi = {{10.1016/j.micpro.2019.102899}},
volume = {{72}},
year = {{2020}},
}