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- 2024
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Mark
TFET Circuit Configurations Operating below 60 mV/dec
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- Contribution to journal › Article
- 2021
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Mark
Power Scaling Laws for Radio Receiver Front Ends
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- Contribution to journal › Article
-
Mark
An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS
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- Contribution to journal › Article
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Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
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- Contribution to journal › Article
- 2020
-
Mark
Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices
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- Contribution to journal › Article
- 2019
-
Mark
A high precision logarithmic-curvature compensated all CMOS voltage reference
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- Contribution to journal › Article
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Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
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- Contribution to journal › Article
- 2015
-
Mark
A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems
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- Contribution to journal › Article
- 2011
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Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
(
- Contribution to journal › Article