Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS

Ghanavati Nejad, Tayebeh ; Farshidi, Ebrahim ; Sjöland, Henrik LU orcid and Kosarian, Abdolnabi (2021) In Analog Integrated Circuits and Signal Processing 107(2). p.319-330
Abstract

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent (γ). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 ppm∘C in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of 6μVV in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 μV/Hz at 100 Hz. The total active area of the design is 0.03 mm2. This... (More)

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent (γ). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 ppm∘C in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of 6μVV in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 μV/Hz at 100 Hz. The total active area of the design is 0.03 mm2. This voltage reference is suitable for low-power low-voltage applications which also require high precision.

(Less)
Please use this url to cite or link to this publication:
author
; ; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
All-CMOS, Curvature-compensation, Low noise, Low power, Low voltage, PSRR, TC, Voltage reference
in
Analog Integrated Circuits and Signal Processing
volume
107
issue
2
pages
319 - 330
publisher
Springer
external identifiers
  • scopus:85101629548
ISSN
0925-1030
DOI
10.1007/s10470-021-01806-1
language
English
LU publication?
yes
id
2246187a-8ab0-4692-afba-6ef4933356d9
date added to LUP
2021-03-16 08:11:32
date last changed
2024-03-21 03:54:18
@article{2246187a-8ab0-4692-afba-6ef4933356d9,
  abstract     = {{<p>In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent (γ). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a temperature coefficient of 3.5 ppm∘C in the range of − 50 to 150 °C, a power supply rejection ratio (PSRR) of − 103 dB at 100 Hz, a line sensitivity of 6μVV in the supply voltage range of 1.3–3 V, a power dissipation of 650nW at 1.3 V supply, and an output noise of 1.7 μV/Hz at 100 Hz. The total active area of the design is 0.03 mm<sup>2</sup>. This voltage reference is suitable for low-power low-voltage applications which also require high precision.</p>}},
  author       = {{Ghanavati Nejad, Tayebeh and Farshidi, Ebrahim and Sjöland, Henrik and Kosarian, Abdolnabi}},
  issn         = {{0925-1030}},
  keywords     = {{All-CMOS; Curvature-compensation; Low noise; Low power; Low voltage; PSRR; TC; Voltage reference}},
  language     = {{eng}},
  month        = {{02}},
  number       = {{2}},
  pages        = {{319--330}},
  publisher    = {{Springer}},
  series       = {{Analog Integrated Circuits and Signal Processing}},
  title        = {{An ultra-low power high-precision logarithmic-curvature compensated all-CMOS voltage reference in 65 nm CMOS}},
  url          = {{http://dx.doi.org/10.1007/s10470-021-01806-1}},
  doi          = {{10.1007/s10470-021-01806-1}},
  volume       = {{107}},
  year         = {{2021}},
}