High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
(2021) In Nature Electronics p.914-914- Abstract
- In-memory computing can be used to overcome the von Neumann bottleneck—the need to shuffle data between separate memory and computational units—and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III–V semiconductor nanowire and a high-κ dielectric (hafnium oxide), which... (More)
- In-memory computing can be used to overcome the von Neumann bottleneck—the need to shuffle data between separate memory and computational units—and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III–V semiconductor nanowire and a high-κ dielectric (hafnium oxide), which provides an oxide layer that can operate either as a vertical transistor selector or a high-performance resistive memory. The resulting 1T1R cells allow Boolean logic operations to be implemented in a single vertical nanowire with a minimal area footprint (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/76b7ea99-13b7-4562-b8a4-5a716d77aa62
- author
- Mamidala, Saketh, Ram LU ; Persson, Karl-Magnus LU ; Irish, Austin LU ; Jönsson, Adam LU ; Timm, Rainer LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2021-12-21
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Vertical 1T1R, In-memory computing, Nanowire, RRAM, 4F2, Vertical MOSFET Selector, cross-point arrays, III-V, Low power
- in
- Nature Electronics
- pages
- 920 pages
- publisher
- Springer Nature
- external identifiers
-
- scopus:85121555596
- ISSN
- 2520-1131
- DOI
- 10.1038/s41928-021-00688-5
- language
- English
- LU publication?
- yes
- id
- 76b7ea99-13b7-4562-b8a4-5a716d77aa62
- date added to LUP
- 2022-01-18 13:58:14
- date last changed
- 2023-11-09 03:13:52
@article{76b7ea99-13b7-4562-b8a4-5a716d77aa62, abstract = {{In-memory computing can be used to overcome the von Neumann bottleneck—the need to shuffle data between separate memory and computational units—and help improve computing performance. Co-integrated vertical transistor selectors (1T) and resistive memory elements (1R) in a 1T1R configuration offer advantages of scalability, speed and energy efficiency in current mass storage applications, and such 1T1R cells could also be potentially used for in-memory computation architectures. Here we show that a vertical transistor and resistive memory can be integrated onto a single vertical indium arsenide nanowire on silicon. The approach relies on an interface between the III–V semiconductor nanowire and a high-κ dielectric (hafnium oxide), which provides an oxide layer that can operate either as a vertical transistor selector or a high-performance resistive memory. The resulting 1T1R cells allow Boolean logic operations to be implemented in a single vertical nanowire with a minimal area footprint}}, author = {{Mamidala, Saketh, Ram and Persson, Karl-Magnus and Irish, Austin and Jönsson, Adam and Timm, Rainer and Wernersson, Lars-Erik}}, issn = {{2520-1131}}, keywords = {{Vertical 1T1R; In-memory computing; Nanowire; RRAM; 4F2; Vertical MOSFET Selector; cross-point arrays; III-V; Low power}}, language = {{eng}}, month = {{12}}, pages = {{914--914}}, publisher = {{Springer Nature}}, series = {{Nature Electronics}}, title = {{High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon}}, url = {{http://dx.doi.org/10.1038/s41928-021-00688-5}}, doi = {{10.1038/s41928-021-00688-5}}, year = {{2021}}, }