Lars-Erik Wernersson
- Department of Electrical and Information Technology
- Nano Electronics
- LTH Profile Area: AI and Digitalization
- LTH Profile Area: Nanoscience and Semiconductor Technology
- NanoLund: Centre for Nanoscience
- LU Profile Area: Light and Materials
- Electromagnetics and Nanoelectronics
- ACT: Advanced Chip Technology
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- 2025
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Mark
Low-frequency noise in ferroelectric III-V vertical gate-all-around FETs
(2025) In IEEE Electron Device Letters
- Contribution to journal › Article
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Mark
Memory State Dynamics in BEOL FeFETs : Impact of Area Ratio on Analog Write Mechanisms and Charging
- Contribution to journal › Article
-
Mark
Interface Characterization of Plasma-Treated InAs Electrodes for Resistive Random-Access Memories Using Capacitance–Voltage Methods
(2025) In Physica Status Solidi (A) Applications and Materials Science
- Contribution to journal › Article
-
Mark
Multi-level vertical III-V nanowire gate-all-rround ferroelectric FETs for in-memory computing
(2025)
- Contribution to conference › Abstract
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Mark
A Reconfigurable Ferroelectric Transistor as An Ultra-Scaled Cell for Low-Power In-Memory Data Processing
- Contribution to journal › Article
- 2024
-
Mark
Source Design of Vertical III-V Nanowire Tunnel Field-Effect Transistors
- Contribution to journal › Article
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Mark
III-V heterostructure tunnel field-effect transistor operation at different temperature regimes
- Contribution to journal › Article
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Mark
A 29.5 GHz Rectifier with 14.5 dB Dynamic Power Range for Energy Harvester Using Vertical Nanowire Tunnel FETs
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
RF Characterization of Ferroelectric MOS Capacitors
- Contribution to journal › Article
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Mark
Multifunctional Reconfigurable Operations in an Ultra-Scaled Ferroelectric Negative Transconductance Transistor
- Contribution to journal › Article
