Electromagnetics and Nanoelectronics
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- 2025
-
Mark
Gate Layout and Process Reliability Co-Optimization in High-Speed Vertical III–V Nanowire Metal-Oxide-Semiconductor Field-Effect Transistor Technology
- Contribution to journal › Article
-
Mark
Prospects of analog in-memory computing using ferroelectric tunnel junctions
- Contribution to journal › Article
-
Mark
Theory and Computation of Substructure Characteristic Modes
- Contribution to journal › Article
-
Mark
Performance Limits for Microstrip Patch Antennas
(2025)
- Thesis › Doctoral thesis (compilation)
-
Mark
Designing objects that are invisible to electromagnetic waves
- Contribution to journal › Article
-
Mark
Scattering computations using a rotationally symmetric solver implemented in open source finite elements
(2025) In Technical Report
- Book/Report › Report
-
Mark
Multi-level vertical III-V nanowire gate-all-around ferroelectric FETs for in-memory computing
(2025)
- Contribution to conference › Abstract
-
Mark
Impact of Layout on the RF Performance of Vertical In–Ga–As Nanowire MOSFETs
- Contribution to journal › Article
-
Mark
Low Resistivity n‐type GaN Ohmic Contacts on GaN Substrates
- Contribution to journal › Article
-
Mark
Sum rules and physical bounds for a particulate slab
(2025) p.253-280
- Chapter in Book/Report/Conference proceeding › Book chapter
