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Multi-Level Analog Computing-In-Memory FeFET-based Unit Cell for Deep Learning

Pereira-Rial ; Dahlberg, Hannes LU ; García-Lesta, D. LU ; Brea, V. M. ; López, P. ; Cabello, D. and Wernersson, Lars Erik LU (2025) 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 In Proceedings - IEEE International Symposium on Circuits and Systems
Abstract

This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS... (More)

This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.

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author
; ; ; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
BEOL, CIM macro, Deep Neural Networks, FeFET
host publication
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
series title
Proceedings - IEEE International Symposium on Circuits and Systems
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
conference location
London, United Kingdom
conference dates
2025-05-25 - 2025-05-28
external identifiers
  • scopus:105010654100
ISSN
0271-4310
ISBN
9798350356830
DOI
10.1109/ISCAS56072.2025.11043743
language
English
LU publication?
yes
additional info
Publisher Copyright: © 2025 IEEE.
id
2a00a4e2-9c7e-4d24-8d2f-bb63dcae1e9c
date added to LUP
2026-01-15 16:27:37
date last changed
2026-01-15 16:27:49
@inproceedings{2a00a4e2-9c7e-4d24-8d2f-bb63dcae1e9c,
  abstract     = {{<p>This paper shows a FeFET-based analog multi-level unit cell for computing-in-memory applications for Deep Neural Networks (DNN). The FeFET-based unit cell performs input-weight multiplication with a Back-End-Of-Line (BEOL) ferro-electric HZO FeFET device on top of standard 180 nm CMOS circuits. The unit cell works with a feedback mechanism which combines an in-house FeFET device to store weights and CMOS transistors underneath to provide outputs in current mode to be integrated over time on a capacitor. Said feedback mechanism compensates for device-to-device variability, and would permit to calibrate a system against time variations, something not usually included in cross-bar solutions. Joint electrical simulations of the FeFET-CMOS circuit are performed with a compact Verilog-A model extracted from the experimental characterization of the FeFET devices. Electrical simulations show that our feedback approach leads to a multi-bit cell with 5-bits of resolution, superior to that of state-of-the-art solutions.</p>}},
  author       = {{Pereira-Rial and Dahlberg, Hannes and García-Lesta, D. and Brea, V. M. and López, P. and Cabello, D. and Wernersson, Lars Erik}},
  booktitle    = {{ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings}},
  isbn         = {{9798350356830}},
  issn         = {{0271-4310}},
  keywords     = {{BEOL; CIM macro; Deep Neural Networks; FeFET}},
  language     = {{eng}},
  month        = {{06}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{Proceedings - IEEE International Symposium on Circuits and Systems}},
  title        = {{Multi-Level Analog Computing-In-Memory FeFET-based Unit Cell for Deep Learning}},
  url          = {{http://dx.doi.org/10.1109/ISCAS56072.2025.11043743}},
  doi          = {{10.1109/ISCAS56072.2025.11043743}},
  year         = {{2025}},
}