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A 5GHz 90-nm CMOS all digital phase-locked loop

Lu, Ping LU and Sjöland, Henrik LU (2011) In Analog Integrated Circuits and Signal Processing 66(1). p.49-59
Abstract
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and... (More)
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
RF, Digitally Controlled Oscillator (DCO), Phase Locked Loop (PLL), Time-to-Digital Converter (TDC), All Digital Phase-Locked Loop (ADPLL), CMOS
in
Analog Integrated Circuits and Signal Processing
volume
66
issue
1
pages
49 - 59
publisher
Springer
external identifiers
  • wos:000286933900006
  • scopus:79951683192
ISSN
0925-1030
DOI
10.1007/s10470-010-9501-9
language
English
LU publication?
yes
id
3534a4c5-fd6a-443a-9630-d1129cde359a (old id 1667537)
date added to LUP
2010-09-07 13:07:17
date last changed
2017-01-01 06:24:59
@article{3534a4c5-fd6a-443a-9630-d1129cde359a,
  abstract     = {An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.},
  author       = {Lu, Ping and Sjöland, Henrik},
  issn         = {0925-1030},
  keyword      = {RF,Digitally Controlled Oscillator (DCO),Phase Locked Loop (PLL),Time-to-Digital Converter (TDC),All Digital Phase-Locked Loop (ADPLL),CMOS},
  language     = {eng},
  number       = {1},
  pages        = {49--59},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A 5GHz 90-nm CMOS all digital phase-locked loop},
  url          = {http://dx.doi.org/10.1007/s10470-010-9501-9},
  volume       = {66},
  year         = {2011},
}