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Graceful Degradation of Reconfigurable Scan Networks

Larsson, Erik LU orcid ; Xiang, Zehang and Murali, Prathamesh (2021) In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29(7). p.1475-1479
Abstract
Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g. IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to fault status of a particular IC. We show how this block enables test for faulty scan- chains, localization of faulty scan-chains, and repair by excluding faulty scan-chains. We made implementations and... (More)
Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g. IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to fault status of a particular IC. We show how this block enables test for faulty scan- chains, localization of faulty scan-chains, and repair by excluding faulty scan-chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area. (Less)
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
volume
29
issue
7
pages
5 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85107215941
ISSN
1063-8210
DOI
10.1109/TVLSI.2021.3076593
language
English
LU publication?
yes
id
1f0db4ca-d866-41e2-8e15-fd1703efdd88
date added to LUP
2021-04-27 11:02:50
date last changed
2024-09-30 14:50:26
@article{1f0db4ca-d866-41e2-8e15-fd1703efdd88,
  abstract     = {{Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g. IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to fault status of a particular IC. We show how this block enables test for faulty scan- chains, localization of faulty scan-chains, and repair by excluding faulty scan-chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.}},
  author       = {{Larsson, Erik and Xiang, Zehang and Murali, Prathamesh}},
  issn         = {{1063-8210}},
  language     = {{eng}},
  month        = {{05}},
  number       = {{7}},
  pages        = {{1475--1479}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  title        = {{Graceful Degradation of Reconfigurable Scan Networks}},
  url          = {{https://lup.lub.lu.se/search/files/97182953/TVLSI21.pdf}},
  doi          = {{10.1109/TVLSI.2021.3076593}},
  volume       = {{29}},
  year         = {{2021}},
}