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Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling

Samii, Soheil; Selkälä, Mikko; Larsson, Erik LU ; Chakrabarty, Krishnendu and Peng, Zebo (2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977
Abstract
Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both... (More)
Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both the test stimuli and the expected test responses during scan-in, launch-and-capture, and scan-out. Furthermore, we allow a unique power model per wrapper-chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Through circuit simulations on ISCAS'89 benchmarks, we demonstrate a high correlation between the real test power dissipation and our cycle-accurate test power model. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be reduced substantially by using the proposed cycle-accurate test power model. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Power constraint, Power estimation, Scan chain, System-on-chip (SoC), Test architecture design, Test power, Test scheduling
in
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
volume
27
issue
5
pages
973 - 977
publisher
Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:42649084344
ISSN
0278-0070
DOI
10.1109/TCAD.2008.917974
language
English
LU publication?
no
id
ab1fb8b5-620d-4582-9e02-de93de3c0491 (old id 2340796)
date added to LUP
2012-02-10 13:45:11
date last changed
2017-08-13 04:34:38
@article{ab1fb8b5-620d-4582-9e02-de93de3c0491,
  abstract     = {Concurrent testing of the cores in a core-based system- on-chip reduces the test application time but increases the test power consumption. Power models, test architecture design, and scheduling algorithms have been proposed to schedule the tests as concurrently as possible while respecting the power budget. The commonly used global peak power model, with a single value capturing the power dissipated by a core when tested, is simple for a scheduling algorithm to handle but is pessimistic. In this paper, we propose a cycle-accurate power model with a power value per clock cycle and a corresponding test architecture design and scheduling algorithm. The power model takes into account the switching activity in the scan chains caused by both the test stimuli and the expected test responses during scan-in, launch-and-capture, and scan-out. Furthermore, we allow a unique power model per wrapper-chain configuration as the activity in a core will be different depending on the number of wrapper chains at a core. Through circuit simulations on ISCAS'89 benchmarks, we demonstrate a high correlation between the real test power dissipation and our cycle-accurate test power model. Extensive experiments on ITC'02 benchmarks and an industrial design show that the testing time can be reduced substantially by using the proposed cycle-accurate test power model.},
  author       = {Samii, Soheil and Selkälä, Mikko and Larsson, Erik and Chakrabarty, Krishnendu and Peng, Zebo},
  issn         = {0278-0070},
  keyword      = {Power constraint,Power estimation,Scan chain,System-on-chip (SoC),Test architecture design,Test power,Test scheduling},
  language     = {eng},
  number       = {5},
  pages        = {973--977},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title        = {Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling},
  url          = {http://dx.doi.org/10.1109/TCAD.2008.917974},
  volume       = {27},
  year         = {2008},
}