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2014
Mark Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) p.1-6
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2012
Mark Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
2011
Mark Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
2008
Mark Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
Samii, Soheil ; Selkälä, Mikko ; Larsson, Erik ^LU ; Chakrabarty, Krishnendu and Peng, Zebo (2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977
- Contribution to journal › Article