Breeta Sengupta (Former)

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2020
Mark Test Cost Reduction of 3D Stacked ICs : Test Planning and Test Flow Selection
Sengupta, Breeta ^LU (2020)
- Thesis › Doctoral thesis (monograph)
2019
Mark Test Flow Selection for Stacked Integrated Circuits
SenGupta, Breeta ^LU ; Nikolov, Dimitar ^LU ; Dash, Assmitra and Larsson, Erik ^LU (2019) In Journal of Electronic Testing: Theory and Applications 35(4). p.425-440
- Contribution to journal › Article
2017
Mark Test Planning for Core-based Integrated Circuits under Power Constraints
SenGupta, Breeta ^LU ; Nikolov, Dimitar ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2017) In Journal of Electronic Testing: Theory and Applications 33(1). p.7-23
- Contribution to journal › Article
2014
Mark Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) IEEE VLSI Test Symposium (VTS) p.1-6
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Test Planning and Test Access Mechanism Design for 3D SICs
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2014) Swedish System on Chip Conference (SSoCC), 2014
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2013
Mark Test Planning for 3D SICs using ILP
Sengupta, Breeta ^LU and Larsson, Erik ^LU (2013) Swedish System-On-Chip Conference (SSoCC), 2013
- Contribution to conference › Paper, not in proceeding
2012
Mark Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) In Journal of Electronic Testing 28(1). p.121-135
- Contribution to journal › Article
Mark Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) 2012 25th International Conference on VLSI Design p.442-447
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
Mark Test Planning for Core-based 3D Stacked ICs under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)
- Contribution to conference › Paper, not in proceeding
2011
Mark Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta ^LU ; Ingelsson, Urban and Larsson, Erik ^LU (2011) 6th International Symposium on Electronic Design, Test and Applications (DELTA 2011) p.72-77
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding

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