Test Planning for 3D SICs using ILP
Sengupta, Breeta LU and Larsson, Erik LU
(2013)
Swedish System-On-Chip Conference (SSoCC), 2013
- Abstract
- In this paper we propose a test planning scheme for corebased
3D stacked integrated circuits where the total test cost for wafer
sort of each individual chip and the test cost of the complete stack
at package test is minimized. We use an Integer Linear Programming
(ILP) model to find the optimal test cost, which is given as the weighted
sum of the test time and the test access mechanism (TAM). As ILP is
time consuming, we use a scheme to bound the test time and the TAM
such that the search space is reduced. The proposed bounding scheme
and the ILP model were applied on several ITC’02 benchmarks and the
results show that optimal solutions were obtained at low... (More) - In this paper we propose a test planning scheme for corebased
3D stacked integrated circuits where the total test cost for wafer
sort of each individual chip and the test cost of the complete stack
at package test is minimized. We use an Integer Linear Programming
(ILP) model to find the optimal test cost, which is given as the weighted
sum of the test time and the test access mechanism (TAM). As ILP is
time consuming, we use a scheme to bound the test time and the TAM
such that the search space is reduced. The proposed bounding scheme
and the ILP model were applied on several ITC’02 benchmarks and the
results show that optimal solutions were obtained at low computation
time. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4305355
- author
- Sengupta, Breeta
LU
and Larsson, Erik
LU
- organization
- publishing date
- 2013
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- Design for Test (DfT), IEEE 1500, Test architecture, Test scheduling, Sessions, Test time, Test cost, 3D Stacked Integrated Circuit (SIC), Through Silicon Via (TSV), Integer Linear Programming (ILP).
- pages
- 8 pages
- conference name
- Swedish System-On-Chip Conference (SSoCC), 2013
- conference location
- Ystad, Sweden
- conference dates
- 2013-05-06 - 2013-05-07
- language
- English
- LU publication?
- yes
- id
- 030f61a4-df8d-456c-9e69-5397c1beadbc (old id 4305355)
- date added to LUP
- 2016-04-04 13:59:03
- date last changed
- 2019-05-24 10:29:54
@misc{030f61a4-df8d-456c-9e69-5397c1beadbc,
abstract = {{In this paper we propose a test planning scheme for corebased<br/><br>
3D stacked integrated circuits where the total test cost for wafer<br/><br>
sort of each individual chip and the test cost of the complete stack<br/><br>
at package test is minimized. We use an Integer Linear Programming<br/><br>
(ILP) model to find the optimal test cost, which is given as the weighted<br/><br>
sum of the test time and the test access mechanism (TAM). As ILP is<br/><br>
time consuming, we use a scheme to bound the test time and the TAM<br/><br>
such that the search space is reduced. The proposed bounding scheme<br/><br>
and the ILP model were applied on several ITC’02 benchmarks and the<br/><br>
results show that optimal solutions were obtained at low computation<br/><br>
time.}},
author = {{Sengupta, Breeta and Larsson, Erik}},
keywords = {{Design for Test (DfT); IEEE 1500; Test architecture; Test scheduling; Sessions; Test time; Test cost; 3D Stacked Integrated Circuit (SIC); Through Silicon Via (TSV); Integer Linear Programming (ILP).}},
language = {{eng}},
title = {{Test Planning for 3D SICs using ILP}},
url = {{https://lup.lub.lu.se/search/files/6252351/4857241.pdf}},
year = {{2013}},
}