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- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Dash, Assmitra and Larsson, Erik LU
(2019)
In Journal of Electronic Testing: Theory and Applications
35(4).
p.425-440
- Contribution to journal › Article
- 2014
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Scenario-Based Network Design for P1687
Ghani Zadegan, Farrokh LU ; Carlsson, Gunnar and Larsson, Erik LU
(2013)
Swedish System-On-Chip Conference (SSoCC), 2013
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D SICs using ILP
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
6th International Symposium on Electronic Design, Test and Applications (DELTA 2011)
p.72-77
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2011)
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)
- Contribution to conference › Paper, not in proceeding
- 2010
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
- Contribution to conference › Paper, not in proceeding
- 1999
-
Mark
Improved computerized perimetric threshold strategies
(1999)
- Thesis › Doctoral thesis (compilation)