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Test Flow Selection for Stacked Integrated Circuits

SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Dash, Assmitra and Larsson, Erik LU (2019) In Journal of Electronic Testing: Theory and Applications (JETTA)
Abstract

Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three... (More)

Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.

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Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
epub
subject
keywords
3D IC, Effective yield, Expected time, IEEE 1500, Quantity, Stacked integrated circuits, Test architecture, Test flow, Test plan, Test time, Yield
in
Journal of Electronic Testing: Theory and Applications (JETTA)
publisher
Springer
external identifiers
  • scopus:85070884880
ISSN
0923-8174
DOI
10.1007/s10836-019-05813-z
language
English
LU publication?
yes
id
dafe07dd-9bb3-4288-a9ac-0861e8ce4d9f
date added to LUP
2019-09-05 09:10:40
date last changed
2019-09-26 04:41:25
@article{dafe07dd-9bb3-4288-a9ac-0861e8ce4d9f,
  abstract     = {<p>Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.</p>},
  author       = {SenGupta, Breeta and Nikolov, Dimitar and Dash, Assmitra and Larsson, Erik},
  issn         = {0923-8174},
  keyword      = {3D IC,Effective yield,Expected time,IEEE 1500,Quantity,Stacked integrated circuits,Test architecture,Test flow,Test plan,Test time,Yield},
  language     = {eng},
  month        = {08},
  publisher    = {Springer},
  series       = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  title        = {Test Flow Selection for Stacked Integrated Circuits},
  url          = {http://dx.doi.org/10.1007/s10836-019-05813-z},
  year         = {2019},
}