1 – 7 of 7
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
(
- Contribution to journal › Article
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
(
- Contribution to journal › Article
- 2012
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article
- 2008
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
(
- Contribution to journal › Article
- 2005
-
Mark
Abort-on-Fail Based Test Scheduling
(
- Contribution to journal › Article
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
(
- Contribution to journal › Article
- 2002
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
(
- Contribution to journal › Article