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- 2019
-
Mark
Test Flow Selection for Stacked Integrated Circuits
SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Dash, Assmitra and Larsson, Erik LU
(2019)
In Journal of Electronic Testing: Theory and Applications
35(4).
p.425-440
- Contribution to journal › Article
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
SenGupta, Breeta LU ; Nikolov, Dimitar LU ; Ingelsson, Urban and Larsson, Erik LU
(2017)
In Journal of Electronic Testing: Theory and Applications
33(1).
p.7-23
- Contribution to journal › Article
- 2012
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU
(2012)
In Journal of Electronic Testing
28(1).
p.121-135
- Contribution to journal › Article
- 2008
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
- Contribution to journal › Article
- 2005
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
Pouget, Julien ; Larsson, Erik LU
and Peng, Zebo
(2005)
In Journal of Electronic Testing
21(6).
p.599-611
- Contribution to journal › Article
-
Mark
Abort-on-Fail Based Test Scheduling
Larsson, Erik LU
; Pouget, Julien
and Peng, Zebo
(2005)
In Journal of Electronic Testing
21(6).
p.651-658
- Contribution to journal › Article
- 2002
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
- Contribution to journal › Article