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Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns

Larsson, Anders; Larsson, Erik LU ; Chakrabarty, Krishnendu; Eles, Petru Ion and Peng, Zebo (2008) Design, Automation, and Test in Europe DATE 2008 In [Host publication title missing] p.188-193
Abstract
Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate... (More)
Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate that theproposed method leads to significant reduction in test data volumeand test time, especially when compared to a method that does notrely on core-level decompression of patterns. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, system-on-chip, test-architecture optimization, test scheduling, test patterns, compression, test access mechanism, TAM, SOC
in
[Host publication title missing]
pages
188 - 193
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
Design, Automation, and Test in Europe DATE 2008
external identifiers
  • scopus:49749098371
ISBN
978-3-9810801-3-
DOI
10.1109/DATE.2008.4484684
language
English
LU publication?
no
id
64ba8c44-eb3e-4e2e-b302-eb0a535e843f (old id 2340979)
date added to LUP
2012-02-10 13:42:26
date last changed
2017-08-27 05:57:38
@inproceedings{64ba8c44-eb3e-4e2e-b302-eb0a535e843f,
  abstract     = {Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate that theproposed method leads to significant reduction in test data volumeand test time, especially when compared to a method that does notrely on core-level decompression of patterns.},
  author       = {Larsson, Anders and Larsson, Erik and Chakrabarty, Krishnendu and Eles, Petru Ion and Peng, Zebo},
  booktitle    = {[Host publication title missing]},
  isbn         = {978-3-9810801-3-},
  keyword      = {testing,system-on-chip,test-architecture optimization,test scheduling,test patterns,compression,test access mechanism,TAM,SOC},
  language     = {eng},
  pages        = {188--193},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns},
  url          = {http://dx.doi.org/10.1109/DATE.2008.4484684},
  year         = {2008},
}