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Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint

Larsson, Erik LU and Edbom, Stina (2007) In IFIP International Federation for Information Processing p.221-244
Abstract
Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number... (More)
Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality. (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, system-on-chip, SOC, test data truncation, test vectors, test access mechanism, TAM
in
IFIP International Federation for Information Processing
pages
221 - 244
publisher
Springer
external identifiers
  • scopus:34548790804
ISBN
978-0-387-73660-0
DOI
10.1007/978-0-387-73661-7
language
English
LU publication?
no
id
8d57c86c-ab15-4d09-be48-107209e4d464 (old id 2340999)
date added to LUP
2012-02-10 13:41:42
date last changed
2017-01-01 08:04:03
@inbook{8d57c86c-ab15-4d09-be48-107209e4d464,
  abstract     = {Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.},
  author       = {Larsson, Erik and Edbom, Stina},
  isbn         = {978-0-387-73660-0},
  keyword      = {testing,system-on-chip,SOC,test data truncation,test vectors,test access mechanism,TAM},
  language     = {eng},
  pages        = {221--244},
  publisher    = {Springer},
  series       = {IFIP International Federation for Information Processing},
  title        = {Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint},
  url          = {http://dx.doi.org/10.1007/978-0-387-73661-7},
  year         = {2007},
}