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Introduction to Advanced System-on-Chip Test Design and Optimization

Larsson, Erik LU (2005) In Frontiers in Electronic Testing
Abstract
Testing ofIntegrated Circuits is important to ensure the production offault-free chips. However, testing is becoming cumbersome andexpensive due to the increasing complexity of these ICs. Technologydevelopment has made it possible to produce chips where a completesystem, with an enormous transistor count, operating at a highclock frequency, is placed on a single die - SOC (System-on-Chip).The device size miniaturization leads to new fault types, theincreasing clock frequencies enforces testing for timing faults,and the increasing transistor count results in a higher number ofpossible fault sites. Testing must handle all these new challengesin an efficient manner having a global system perspective.Test design is applied to make a system... (More)
Testing ofIntegrated Circuits is important to ensure the production offault-free chips. However, testing is becoming cumbersome andexpensive due to the increasing complexity of these ICs. Technologydevelopment has made it possible to produce chips where a completesystem, with an enormous transistor count, operating at a highclock frequency, is placed on a single die - SOC (System-on-Chip).The device size miniaturization leads to new fault types, theincreasing clock frequencies enforces testing for timing faults,and the increasing transistor count results in a higher number ofpossible fault sites. Testing must handle all these new challengesin an efficient manner having a global system perspective.Test design is applied to make a system testable. In a modularcore-based environment where blocks of reusable logic, the socalled cores, are integrated to a system, test design for each coreinclude: test method selection, test data (stimuli and responses)generation (ATPG), definition of test data storage and partitioning[off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST(Built-In Self-Test)], wrapper selection and design (IEEE std1500), TAM (test access mechanism) design, and test schedulingminimizing a cost function whilst considering limitations andconstraint. A system test design perspective that takes all theissues above into account is required in order to develop aglobally optimized solution.SOC test design and its optimization is the topic of this book. Itgives an introduction to testing, describes the problems related toSOC testing, discusses the modeling granularity and theimplementation into EDA (electronic design automation) tools. Thebook is divided into three sections: i) test concepts, ii) SOCdesign for test, and iii) SOC test applications. The first partcovers an introduction into test problems including faults, faulttypes, design-flow, design-for-test techniques such as scan-testingand Boundary Scan. The second part of the book discusses SOCrelated problems such as system modeling, test conflicts, powerconsumption, test access mechanism design, test scheduling anddefect-oriented scheduling. Finally, the third part focuses on SOCapplications, such as integrated test scheduling and TAM design,defect-oriented scheduling, and integrating test design with thecore selection process. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Book/Report
publication status
published
subject
keywords
testing, system-on-chip, ATE, ATPG, IEEE std 1500, test access mechanism, TAM, optimization
in
Frontiers in Electronic Testing
publisher
Springer
ISBN
1-4020-3207-2
DOI
10.1007/b135763
language
English
LU publication?
no
id
b40eb618-be08-41f7-9d29-c406b2536620 (old id 2341049)
date added to LUP
2012-02-10 13:36:57
date last changed
2016-06-29 08:58:30
@book{b40eb618-be08-41f7-9d29-c406b2536620,
  abstract     = {Testing ofIntegrated Circuits is important to ensure the production offault-free chips. However, testing is becoming cumbersome andexpensive due to the increasing complexity of these ICs. Technologydevelopment has made it possible to produce chips where a completesystem, with an enormous transistor count, operating at a highclock frequency, is placed on a single die - SOC (System-on-Chip).The device size miniaturization leads to new fault types, theincreasing clock frequencies enforces testing for timing faults,and the increasing transistor count results in a higher number ofpossible fault sites. Testing must handle all these new challengesin an efficient manner having a global system perspective.Test design is applied to make a system testable. In a modularcore-based environment where blocks of reusable logic, the socalled cores, are integrated to a system, test design for each coreinclude: test method selection, test data (stimuli and responses)generation (ATPG), definition of test data storage and partitioning[off-chip as ATE (Automatic Test Equipment) and/or on-chip as BIST(Built-In Self-Test)], wrapper selection and design (IEEE std1500), TAM (test access mechanism) design, and test schedulingminimizing a cost function whilst considering limitations andconstraint. A system test design perspective that takes all theissues above into account is required in order to develop aglobally optimized solution.SOC test design and its optimization is the topic of this book. Itgives an introduction to testing, describes the problems related toSOC testing, discusses the modeling granularity and theimplementation into EDA (electronic design automation) tools. Thebook is divided into three sections: i) test concepts, ii) SOCdesign for test, and iii) SOC test applications. The first partcovers an introduction into test problems including faults, faulttypes, design-flow, design-for-test techniques such as scan-testingand Boundary Scan. The second part of the book discusses SOCrelated problems such as system modeling, test conflicts, powerconsumption, test access mechanism design, test scheduling anddefect-oriented scheduling. Finally, the third part focuses on SOCapplications, such as integrated test scheduling and TAM design,defect-oriented scheduling, and integrating test design with thecore selection process.},
  author       = {Larsson, Erik},
  isbn         = {1-4020-3207-2},
  keyword      = {testing,system-on-chip,ATE,ATPG,IEEE std 1500,test access mechanism,TAM,optimization},
  language     = {eng},
  publisher    = {Springer},
  series       = {Frontiers in Electronic Testing},
  title        = {Introduction to Advanced System-on-Chip Test Design and Optimization},
  url          = {http://dx.doi.org/10.1007/b135763},
  year         = {2005},
}