Advanced

Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint

Larsson, Erik LU and Edbom, Stina (2005) IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005} p.429-434
Abstract
The increasingtest data volume required to ensure high test quality when testinga System-on-Chip is becoming a problem since it (the test datavolume) must fit the ATE (Automatic Test Equipment) memory. In thispaper, we (1) define a test quality metric based on fault coverage,defect probability and number of applied test vectors, and (2) atest data truncation scheme. The truncation scheme combines (1)test data (vector) selection for each core based on our metric, and(2) scheduling of the execution of the selected test data, in sucha way that the system test quality is maximized, while the selectedtest data is guaranteed to fit the ATEs memory. We have implementedthe technique and the experimental results, produced at reasonableCPU times, on... (More)
The increasingtest data volume required to ensure high test quality when testinga System-on-Chip is becoming a problem since it (the test datavolume) must fit the ATE (Automatic Test Equipment) memory. In thispaper, we (1) define a test quality metric based on fault coverage,defect probability and number of applied test vectors, and (2) atest data truncation scheme. The truncation scheme combines (1)test data (vector) selection for each core based on our metric, and(2) scheduling of the execution of the selected test data, in sucha way that the system test quality is maximized, while the selectedtest data is guaranteed to fit the ATEs memory. We have implementedthe technique and the experimental results, produced at reasonableCPU times, on several ITC02 benchmarks show that high test qualitycan be achieved by a careful selection of testdata. (Less)
Please use this url to cite or link to this publication:
author
publishing date
type
Contribution to conference
publication status
published
subject
keywords
testing, test scheduling, test quality optimization, ATE memory
pages
429 - 434
conference name
IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005}
language
English
LU publication?
no
id
047c3152-747b-4fd0-8261-67656f8a88b9 (old id 2341055)
alternative location
http://www.ida.liu.se/labs/eslab/publications/pap/db/erila_vlsi_soc05.final.pdf
date added to LUP
2012-02-10 13:37:43
date last changed
2016-08-23 16:09:24
@misc{047c3152-747b-4fd0-8261-67656f8a88b9,
  abstract     = {The increasingtest data volume required to ensure high test quality when testinga System-on-Chip is becoming a problem since it (the test datavolume) must fit the ATE (Automatic Test Equipment) memory. In thispaper, we (1) define a test quality metric based on fault coverage,defect probability and number of applied test vectors, and (2) atest data truncation scheme. The truncation scheme combines (1)test data (vector) selection for each core based on our metric, and(2) scheduling of the execution of the selected test data, in sucha way that the system test quality is maximized, while the selectedtest data is guaranteed to fit the ATEs memory. We have implementedthe technique and the experimental results, produced at reasonableCPU times, on several ITC02 benchmarks show that high test qualitycan be achieved by a careful selection of testdata.},
  author       = {Larsson, Erik and Edbom, Stina},
  keyword      = {testing,test scheduling,test quality optimization,ATE memory},
  language     = {eng},
  pages        = {429--434},
  title        = {Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint},
  year         = {2005},
}