The Design and Optimization of SOC Test Solutions
(2001) IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 p.523-530- Abstract
- We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341104
- author
- Larsson, Erik LU ; Peng, Zebo and Carlsson, Gunnar
- publishing date
- 2001
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- system-on-chip, testing, test conflicts, optimized design, embedded systems
- host publication
- [Host publication title missing]
- pages
- 523 - 530
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001
- conference location
- San Jose, CA, United States
- conference dates
- 2001-11-04 - 2001-11-08
- external identifiers
-
- scopus:0035209105
- ISSN
- 1092-3152
- ISBN
- 0-7803-7247-6
- DOI
- 10.1109/ICCAD.2001.968697
- language
- English
- LU publication?
- no
- id
- 0d2eb1e3-11fc-40e5-b729-5605d0a54917 (old id 2341104)
- date added to LUP
- 2016-04-01 15:24:15
- date last changed
- 2022-02-05 01:06:01
@inproceedings{0d2eb1e3-11fc-40e5-b729-5605d0a54917, abstract = {{We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.}}, author = {{Larsson, Erik and Peng, Zebo and Carlsson, Gunnar}}, booktitle = {{[Host publication title missing]}}, isbn = {{0-7803-7247-6}}, issn = {{1092-3152}}, keywords = {{system-on-chip; testing; test conflicts; optimized design; embedded systems}}, language = {{eng}}, pages = {{523--530}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{The Design and Optimization of SOC Test Solutions}}, url = {{http://dx.doi.org/10.1109/ICCAD.2001.968697}}, doi = {{10.1109/ICCAD.2001.968697}}, year = {{2001}}, }