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The Design and Optimization of SOC Test Solutions

Larsson, Erik LU ; Peng, Zebo and Carlsson, Gunnar (2001) IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001 In [Host publication title missing] p.523-530
Abstract
We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
system-on-chip, testing, test conflicts, optimized design, embedded systems
in
[Host publication title missing]
pages
523 - 530
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001
external identifiers
  • scopus:0035209105
ISSN
1092-3152
ISBN
0-7803-7247-6
DOI
language
English
LU publication?
no
id
0d2eb1e3-11fc-40e5-b729-5605d0a54917 (old id 2341104)
date added to LUP
2012-02-10 13:31:38
date last changed
2018-05-29 12:15:33
@inproceedings{0d2eb1e3-11fc-40e5-b729-5605d0a54917,
  abstract     = {We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.},
  author       = {Larsson, Erik and Peng, Zebo and Carlsson, Gunnar},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7803-7247-6},
  issn         = {1092-3152},
  keyword      = {system-on-chip,testing,test conflicts,optimized design,embedded systems},
  language     = {eng},
  pages        = {523--530},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {The Design and Optimization of SOC Test Solutions},
  url          = {http://dx.doi.org/},
  year         = {2001},
}