Advanced

Power Constrained Preemptive TAM Scheduling

Larsson, Erik LU and Fujiwara, Hideo (2002) 7th IEEE European Test Workshop,2002 In [Host publication title missing] p.119-119
Abstract
We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the test clock. We model the scheduling problem as a Bin-packing problem and we discuss the transformations: (1) TAM-time and (2) power-time and the possibilities to achieve an optimal solution and the limitations. We have implemented our proposed preemptive TAM scheduling algorithm and through experiments we demonstrate its efficiency.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
scan-chain partitioning, core-based systems, power constraint, test access mechanism, TAM, preemptive TAM scheduling
in
[Host publication title missing]
pages
119 - 119
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
7th IEEE European Test Workshop,2002
external identifiers
  • scopus:84931351424
ISSN
1530-1877
ISBN
0-7695-1715-3
DOI
10.1109/ETW.2002.1029648
language
English
LU publication?
no
id
8034575f-e385-48b3-8668-1ec9e34fdb22 (old id 2341111)
date added to LUP
2012-02-10 13:32:01
date last changed
2017-04-23 04:15:09
@inproceedings{8034575f-e385-48b3-8668-1ec9e34fdb22,
  abstract     = {We integrate scan-chain partitioning and preemptive test access mechanism (TAM) scheduling for core-based systems under power constraint. We also outline a flexible power conscious test wrapper to increase the flexibility in the scheduling process by (1) allowing several different bandwidths at cores and (2) controlling the cores test power consumption, which makes it possible to increase the test clock. We model the scheduling problem as a Bin-packing problem and we discuss the transformations: (1) TAM-time and (2) power-time and the possibilities to achieve an optimal solution and the limitations. We have implemented our proposed preemptive TAM scheduling algorithm and through experiments we demonstrate its efficiency.},
  author       = {Larsson, Erik and Fujiwara, Hideo},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-1715-3},
  issn         = {1530-1877},
  keyword      = {scan-chain partitioning,core-based systems,power constraint,test access mechanism,TAM,preemptive TAM scheduling},
  language     = {eng},
  pages        = {119--119},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Power Constrained Preemptive TAM Scheduling},
  url          = {http://dx.doi.org/10.1109/ETW.2002.1029648},
  year         = {2002},
}