A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
(2003) International Test Conference ITC 2003 p.1135-1135- Abstract
- This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341135
- author
- Larsson, Erik LU and Peng, Zebo
- publishing date
- 2003
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- test access mechanisms, TAM, test scheduling, wrapper configuration, TAM routing, wrapper logic, test power consumption, preemptive scheduling
- host publication
- [Host publication title missing]
- pages
- 1135 - 1135
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- International Test Conference ITC 2003
- conference location
- Charlotte, NC, United States
- conference dates
- 2003-09-30 - 2003-10-02
- external identifiers
-
- scopus:0142215922
- language
- English
- LU publication?
- no
- id
- 9bcbf3eb-29e7-460f-a452-c089075287de (old id 2341135)
- alternative location
- http://www.ida.liu.se/labs/eslab/publications/pap/db/itc03.pdf
- date added to LUP
- 2016-04-04 12:19:54
- date last changed
- 2022-01-29 23:14:15
@inproceedings{9bcbf3eb-29e7-460f-a452-c089075287de, abstract = {{This paper presents a novel reconfigurable powerconscious core test wrapper and discusses its application to optimal power-constrained SOC (system-on-chip) test scheduling. The advantage with the proposed wrapper is that at each core it allows (1) a exible TAM (test access mechanism) bandwidths, and (2) a possibility to select the appropriate test power consumption. Our scheduling technique, an extension of a preemptive scheduling approach,produces optimal solutions in respect to test time, and selects wrapper configurations in a systematic way that implicitly minimizes the TAM routing and the wrapper logic. Experimental results show the efficiency of our approach.}}, author = {{Larsson, Erik and Peng, Zebo}}, booktitle = {{[Host publication title missing]}}, keywords = {{test access mechanisms; TAM; test scheduling; wrapper configuration; TAM routing; wrapper logic; test power consumption; preemptive scheduling}}, language = {{eng}}, pages = {{1135--1135}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling}}, url = {{http://www.ida.liu.se/labs/eslab/publications/pap/db/itc03.pdf}}, year = {{2003}}, }