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An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint

Edbom, Stina and Larsson, Erik LU (2004) 2004 IEEE Asian Test Symposium ATS 2004 In [Host publication title missing] p.254-257
Abstract
The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.
Please use this url to cite or link to this publication:
author
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
testing, fault coverage, defect probabilities, embedded systems
in
[Host publication title missing]
pages
254 - 257
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2004 IEEE Asian Test Symposium ATS 2004
external identifiers
  • scopus:13244259156
ISSN
1081-7735
ISBN
0-7695-2235-1
DOI
10.1109/ATS.2004.24
language
English
LU publication?
no
id
1fc5538d-2b59-4239-9189-97b5cf0aac02 (old id 2341164)
date added to LUP
2012-02-10 13:26:44
date last changed
2017-02-19 04:04:37
@inproceedings{1fc5538d-2b59-4239-9189-97b5cf0aac02,
  abstract     = {The quality of test is highly related to the number of faults that can be detected during the testing (fault coverage) and the defect probability of each testable unit. High test quality is reached by applying an excessive number of good test vectors, however, such a high test data volume can be problematic to fit in the ATE's (automatic test equipment) limited memory. We therefore propose, for core-based designs, a scheme that selects test vectors for each core, and schedule the test vectors in such a way that the test quality is maximized under a given test time constraint given by the ATE memory depth.},
  author       = {Edbom, Stina and Larsson, Erik},
  booktitle    = {[Host publication title missing]},
  isbn         = {0-7695-2235-1},
  issn         = {1081-7735},
  keyword      = {testing,fault coverage,defect probabilities,embedded systems},
  language     = {eng},
  pages        = {254--257},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint},
  url          = {http://dx.doi.org/10.1109/ATS.2004.24},
  year         = {2004},
}