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A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS

Lu, Ping LU and Andreani, Pietro LU (2010) NORCHIP Conference, 2010
Abstract
A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
[Host publication title missing]
pages
4 pages
conference name
NORCHIP Conference, 2010
conference location
Tampere, Finland
conference dates
2010-11-15 - 2010-11-16
external identifiers
  • scopus:78751515701
ISBN
978-1-4244-8972-5
DOI
10.1109/NORCHIP.2010.5669467
language
English
LU publication?
yes
id
fd719782-6da5-4df9-beb3-63da9080523c (old id 2437188)
date added to LUP
2016-04-04 14:04:49
date last changed
2025-04-04 13:58:46
@inproceedings{fd719782-6da5-4df9-beb3-63da9080523c,
  abstract     = {{A Vernier Gate-Ring-Oscillator (GRO) Time to Digital Converter (TDC) is proposed and implemented in 90-nm CMOS process technology. It utilizes two GRO chains as the delay lines. The time resolution is determined by the difference between two delays, so not limited by the process. Moreover, the quantization noise can be first-order shaped by the gated behavior in the oscillators, which further improves the in-band TDC noise contribution for an ADPLL. Operating at 1.2-V supply with 250MHz clock, the chip achieves a less-than-10ps coarse resolution (varies with digital control bits) and consumes only 3.6-mA.}},
  author       = {{Lu, Ping and Andreani, Pietro}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{978-1-4244-8972-5}},
  language     = {{eng}},
  title        = {{A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS}},
  url          = {{http://dx.doi.org/10.1109/NORCHIP.2010.5669467}},
  doi          = {{10.1109/NORCHIP.2010.5669467}},
  year         = {{2010}},
}