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A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs

Tan, Siyu LU ; Palm, Mattias ; Mastantuono, Daniele ; Strandberg, Roland ; Sundström, Lars ; Mattisson, Sven and Andreani, Piero LU (2020) 2020 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
Abstract
This paper analyzes the bit conversion errors in high speed SAR ADCs and proposes a design method to minimize their impact on the ADC performance. By removing the SR latch from the output stage of the differential comparator, while using only one comparator output to generate the differential signals for the internal capacitive DAC, sparkle-code errors are avoided, and conversion errors from a previous bit conversion due to memory effects in the SR latch are eliminated.

A 10-bit synchronous SAR ADC has been modeled in MATLAB and subsequently implemented at the circuit level in a 22nm FD-SOI CMOS technology. The ADC shows a graceful SNDR degradation at increased sampling frequencies, vastly improving the ADC performance compared to... (More)
This paper analyzes the bit conversion errors in high speed SAR ADCs and proposes a design method to minimize their impact on the ADC performance. By removing the SR latch from the output stage of the differential comparator, while using only one comparator output to generate the differential signals for the internal capacitive DAC, sparkle-code errors are avoided, and conversion errors from a previous bit conversion due to memory effects in the SR latch are eliminated.

A 10-bit synchronous SAR ADC has been modeled in MATLAB and subsequently implemented at the circuit level in a 22nm FD-SOI CMOS technology. The ADC shows a graceful SNDR degradation at increased sampling frequencies, vastly improving the ADC performance compared to when sparkle-code errors, or conversion errors due to an invalid comparator output, are allowed to occur.
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author
; ; ; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
2020 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC) - NORCHIP and International Symposium of System-on-Chip (SoC)
pages
6 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2020 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)
conference location
OSLO, Norway
conference dates
2020-10-27 - 2020-10-28
external identifiers
  • scopus:85099791138
ISBN
978-1-7281-9226-0
978-1-7281-9227-7
DOI
10.1109/NorCAS51424.2020.9264999
language
English
LU publication?
yes
id
2564a196-eb38-43d0-902a-8a11005cb065
date added to LUP
2020-11-24 10:57:38
date last changed
2024-10-03 13:45:42
@inproceedings{2564a196-eb38-43d0-902a-8a11005cb065,
  abstract     = {{This paper analyzes the bit conversion errors in high speed SAR ADCs and proposes a design method to minimize their impact on the ADC performance. By removing the SR latch from the output stage of the differential comparator, while using only one comparator output to generate the differential signals for the internal capacitive DAC, sparkle-code errors are avoided, and conversion errors from a previous bit conversion due to memory effects in the SR latch are eliminated.<br/><br/>A 10-bit synchronous SAR ADC has been modeled in MATLAB and subsequently implemented at the circuit level in a 22nm FD-SOI CMOS technology. The ADC shows a graceful SNDR degradation at increased sampling frequencies, vastly improving the ADC performance compared to when sparkle-code errors, or conversion errors due to an invalid comparator output, are allowed to occur.<br/>}},
  author       = {{Tan, Siyu and Palm, Mattias and Mastantuono, Daniele and Strandberg, Roland and Sundström, Lars and Mattisson, Sven and Andreani, Piero}},
  booktitle    = {{2020 IEEE Nordic Circuits and Systems Conference (NORCAS) : NORCHIP and International Symposium of System-on-Chip (SoC)}},
  isbn         = {{978-1-7281-9226-0}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs}},
  url          = {{http://dx.doi.org/10.1109/NorCAS51424.2020.9264999}},
  doi          = {{10.1109/NorCAS51424.2020.9264999}},
  year         = {{2020}},
}