A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS
(2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 5. p.4947-4950- Abstract
- An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/602927
- author
- Guo, Zhan LU and Nilsson, Peter LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.
- volume
- 5
- pages
- 4947 - 4950
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2005
- conference location
- Kobe, Japan
- conference dates
- 2005-05-23 - 2005-05-26
- external identifiers
-
- wos:000232002404193
- scopus:47049120210
- ISBN
- 0-7803-8834-8
- DOI
- 10.1109/ISCAS.2005.1465743
- language
- English
- LU publication?
- yes
- id
- 310653b7-97d9-4a64-b860-be17e621a38f (old id 602927)
- date added to LUP
- 2016-04-04 13:03:39
- date last changed
- 2022-01-29 23:41:19
@inproceedings{310653b7-97d9-4a64-b860-be17e621a38f, abstract = {{An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.}}, author = {{Guo, Zhan and Nilsson, Peter}}, booktitle = {{IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.}}, isbn = {{0-7803-8834-8}}, language = {{eng}}, pages = {{4947--4950}}, title = {{A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS}}, url = {{http://dx.doi.org/10.1109/ISCAS.2005.1465743}}, doi = {{10.1109/ISCAS.2005.1465743}}, volume = {{5}}, year = {{2005}}, }