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A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems

Gangarajaiah, Rakesh LU ; Liu, Liang LU ; Stala, Michal LU ; Nilsson, Peter LU and Edfors, Ove LU (2013) European Conference on Circuit Theory and Design (ECCTD 2013)
Abstract
This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.
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author
organization
publishing date
type
Contribution to conference
publication status
published
subject
pages
4 pages
conference name
European Conference on Circuit Theory and Design (ECCTD 2013)
external identifiers
  • scopus:84892629955
language
English
LU publication?
yes
id
8e361bcb-08c1-4180-baf5-8269eb013e34 (old id 4023949)
date added to LUP
2013-12-10 11:23:54
date last changed
2017-03-26 04:39:36
@misc{8e361bcb-08c1-4180-baf5-8269eb013e34,
  abstract     = {This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77mm2 and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 219mW.},
  author       = {Gangarajaiah, Rakesh and Liu, Liang and Stala, Michal and Nilsson, Peter and Edfors, Ove},
  language     = {eng},
  pages        = {4},
  title        = {A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems},
  year         = {2013},
}