Advanced

Test Planning for 3D Stacked ICs with Through-Silicon Vias

Sengupta, Breeta LU ; Ingelsson, Urban and Larsson, Erik LU (2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
conference name
Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
language
English
LU publication?
no
id
b4182574-5c1d-4231-9073-91bcf75fa5de (old id 4305356)
date added to LUP
2014-02-13 10:47:07
date last changed
2016-04-16 12:22:27
@misc{b4182574-5c1d-4231-9073-91bcf75fa5de,
  author       = {Sengupta, Breeta and Ingelsson, Urban and Larsson, Erik},
  language     = {eng},
  title        = {Test Planning for 3D Stacked ICs with Through-Silicon Vias},
  year         = {2011},
}