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A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

Mohammadi, Babak LU ; Andersson, Oskar LU ; Meinerzhagen, Pascal ; Sherazi, Syed Muhammad Yasser LU ; Burg, Andreas and Rodrigues, Joachim LU (2014) FTFC
Abstract
The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power
Please use this url to cite or link to this publication:
author
; ; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
host publication
[Host publication title missing]
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
FTFC
conference location
Monaco
conference dates
2014-05-04 - 2014-05-06
external identifiers
  • wos:000356507700026
  • scopus:84903834605
DOI
10.1109/FTFC.2014.6828618
language
English
LU publication?
yes
id
7459b1a8-1e75-4ea4-8c0e-eba79c76d4f7 (old id 4436941)
date added to LUP
2016-04-04 11:41:35
date last changed
2025-04-04 15:13:14
@inproceedings{7459b1a8-1e75-4ea4-8c0e-eba79c76d4f7,
  abstract     = {{The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power}},
  author       = {{Mohammadi, Babak and Andersson, Oskar and Meinerzhagen, Pascal and Sherazi, Syed Muhammad Yasser and Burg, Andreas and Rodrigues, Joachim}},
  booktitle    = {{[Host publication title missing]}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS}},
  url          = {{http://dx.doi.org/10.1109/FTFC.2014.6828618}},
  doi          = {{10.1109/FTFC.2014.6828618}},
  year         = {{2014}},
}