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A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

Axholt, Andreas LU and Sjöland, Henrik LU (2014) In Analog Integrated Circuits and Signal Processing 80(1). p.23-32
Abstract
This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to... (More)
This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25 GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than −10 dB between 57.5 and 60.8 GHz, a 15 dB voltage gain, and a 9 dB noise figure. Two-tone measurements show −12.5 dBm IIP3, 29 dBm IIP2, and −24 dBm ICP1. The PC-PLL phase noise is −105 dBc/Hz at 1 MHz offset from a 20 GHz carrier, and the phase of the received 60 GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80 mA from a 1.2 V supply, and measures 1,400 μm × 660 μm (900 μm × 500 μm excluding pads) including LNAs, mixers, and PC-PLL in a 90 nm RF CMOS process. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
Analog Integrated Circuits and Signal Processing
volume
80
issue
1
pages
23 - 32
publisher
Springer
external identifiers
  • wos:000336384500003
  • scopus:84902161826
ISSN
0925-1030
DOI
10.1007/s10470-014-0301-5
project
EIT_HSWC:RFNano RF tranceivers and nano devices
language
English
LU publication?
yes
id
76521998-95a8-4429-aec1-3dfe7191f1f3 (old id 4452066)
date added to LUP
2014-06-02 14:19:57
date last changed
2017-01-01 05:21:27
@article{76521998-95a8-4429-aec1-3dfe7191f1f3,
  abstract     = {This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25 GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than −10 dB between 57.5 and 60.8 GHz, a 15 dB voltage gain, and a 9 dB noise figure. Two-tone measurements show −12.5 dBm IIP3, 29 dBm IIP2, and −24 dBm ICP1. The PC-PLL phase noise is −105 dBc/Hz at 1 MHz offset from a 20 GHz carrier, and the phase of the received 60 GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80 mA from a 1.2 V supply, and measures 1,400 μm × 660 μm (900 μm × 500 μm excluding pads) including LNAs, mixers, and PC-PLL in a 90 nm RF CMOS process.},
  author       = {Axholt, Andreas and Sjöland, Henrik},
  issn         = {0925-1030},
  language     = {eng},
  number       = {1},
  pages        = {23--32},
  publisher    = {Springer},
  series       = {Analog Integrated Circuits and Signal Processing},
  title        = {A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays},
  url          = {http://dx.doi.org/10.1007/s10470-014-0301-5},
  volume       = {80},
  year         = {2014},
}