A low logic depth complex multiplier
(1998) European Solid-State Circuits Conference (ESSCIRC), 1998 p.204-207- Abstract
- A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1225670
- author
- Berkeman, Anders LU ; Öwall, Viktor LU and Torkelson, Mats LU
- organization
- publishing date
- 1998
- type
- Contribution to conference
- publication status
- published
- subject
- pages
- 204 - 207
- conference name
- European Solid-State Circuits Conference (ESSCIRC), 1998
- conference location
- Hague, Netherlands
- conference dates
- 1998-09-22 - 1998-09-24
- external identifiers
-
- scopus:0347073324
- language
- English
- LU publication?
- yes
- id
- 44d1cce2-29cc-42cd-82ad-ef73e6b1d7e4 (old id 1225670)
- date added to LUP
- 2016-04-04 14:40:29
- date last changed
- 2022-02-14 01:43:22
@misc{44d1cce2-29cc-42cd-82ad-ef73e6b1d7e4, abstract = {{A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.}}, author = {{Berkeman, Anders and Öwall, Viktor and Torkelson, Mats}}, language = {{eng}}, pages = {{204--207}}, title = {{A low logic depth complex multiplier}}, url = {{https://lup.lub.lu.se/search/files/6414536/1228090}}, year = {{1998}}, }