III-V compound semiconductor transistors-from planar to nanowire structures
(2014) In MRS Bulletin 39(8). p.668-677- Abstract
- Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such... (More)
- Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs-from planar to nanowire devices-integrated on a silicon platform to make these technologies suitable for future CMOS applications. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4725948
- author
- Riel, Heike ; Wernersson, Lars-Erik LU ; Hong, Minghwei and del Alamo, Jesus A.
- organization
- publishing date
- 2014
- type
- Contribution to journal
- publication status
- published
- subject
- in
- MRS Bulletin
- volume
- 39
- issue
- 8
- pages
- 668 - 677
- publisher
- Materials Research Society
- external identifiers
-
- wos:000341107900008
- scopus:84915753352
- ISSN
- 1938-1425
- DOI
- 10.1557/mrs.2014.137
- language
- English
- LU publication?
- yes
- id
- 6c624c11-1cb7-49ac-94c7-bcfe30db70b0 (old id 4725948)
- date added to LUP
- 2016-04-01 09:49:33
- date last changed
- 2025-04-04 14:13:52
@article{6c624c11-1cb7-49ac-94c7-bcfe30db70b0,
abstract = {{Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III-V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III-V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III-V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III-V MOSFETs and heterostructure TFETs-from planar to nanowire devices-integrated on a silicon platform to make these technologies suitable for future CMOS applications.}},
author = {{Riel, Heike and Wernersson, Lars-Erik and Hong, Minghwei and del Alamo, Jesus A.}},
issn = {{1938-1425}},
language = {{eng}},
number = {{8}},
pages = {{668--677}},
publisher = {{Materials Research Society}},
series = {{MRS Bulletin}},
title = {{III-V compound semiconductor transistors-from planar to nanowire structures}},
url = {{http://dx.doi.org/10.1557/mrs.2014.137}},
doi = {{10.1557/mrs.2014.137}},
volume = {{39}},
year = {{2014}},
}