Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method
(2013) 43rd Conference on European Solid-State Device Research p.53-56- Abstract
- The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/4810264
- author
- Johansson, Sofia LU ; Mo, Jiongjiong LU and Lind, Erik LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)
- pages
- 53 - 56
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 43rd Conference on European Solid-State Device Research
- conference dates
- 2013-09-16 - 2013-09-20
- external identifiers
-
- wos:000342231600011
- scopus:84902205933
- ISSN
- 1930-8876
- language
- English
- LU publication?
- yes
- id
- fa30dab7-5c75-409f-a036-964dc99554ba (old id 4810264)
- date added to LUP
- 2016-04-01 14:43:21
- date last changed
- 2024-01-10 07:46:20
@inproceedings{fa30dab7-5c75-409f-a036-964dc99554ba, abstract = {{The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.}}, author = {{Johansson, Sofia and Mo, Jiongjiong and Lind, Erik}}, booktitle = {{2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)}}, issn = {{1930-8876}}, language = {{eng}}, pages = {{53--56}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method}}, year = {{2013}}, }