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A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI

Palm, Mattias ; Mastantuono, Daniele ; Strandberg, Roland ; Sundström, Lars and Mattisson, Sven LU (2017) 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
Abstract
This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.
Please use this url to cite or link to this publication:
author
; ; ; and
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
buffer linearization, time-interleaved pipelined-SAR converter, multiband mobile communication receiver, super-source follower, drain bias resistor, sampling time mismatch, SFDR, gain mismatch correction, FD-SOI, input buffer, TI pipelined-SAR converter, specific bias current, common sample and hold circuit, SNR, SNDR, FOM, voltage references, bandgap, clock circuitry, subADC voltage reference
host publication
ESSCIRC 2017 : 43rd IEEE European Solid State Circuits Conference - 43rd IEEE European Solid State Circuits Conference
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
conference location
Leuven, Belgium
conference dates
2017-09-11 - 2017-09-14
external identifiers
  • scopus:85040563743
ISBN
978-1-5090-5025-3
978-1-5090-5026-0
DOI
10.1109/ESSCIRC.2017.8094555
language
English
LU publication?
no
id
5a90c033-8c03-462b-8b09-f628c23e0daa
date added to LUP
2019-04-30 07:50:02
date last changed
2024-01-01 02:21:43
@inproceedings{5a90c033-8c03-462b-8b09-f628c23e0daa,
  abstract     = {{This paper presents a time-interleaved pipelined-SAR converter targeting a multi-band mobile communication receiver. The input buffer is based on a super-source follower and linearized by selecting a specific bias current and drain bias resistor. Time interleaved sampling time mismatch is resolved by using a common sample and hold circuit, and gain mismatch is corrected by fine tuning respective subADC voltage reference. The prototype is implemented in 28 nm FD-SOI and achieves an SNR/SNDR/SFDR/FOM of 56.9/56.1/65/154 dB, consuming 89 mW including input buffer, voltage references, bias with bandgap and clock circuitry.}},
  author       = {{Palm, Mattias and Mastantuono, Daniele and Strandberg, Roland and Sundström, Lars and Mattisson, Sven}},
  booktitle    = {{ESSCIRC 2017 : 43rd IEEE European Solid State Circuits Conference}},
  isbn         = {{978-1-5090-5025-3}},
  keywords     = {{buffer linearization; time-interleaved pipelined-SAR converter; multiband mobile communication receiver; super-source follower; drain bias resistor; sampling time mismatch; SFDR; gain mismatch correction; FD-SOI; input buffer; TI pipelined-SAR converter; specific bias current; common sample and hold circuit; SNR; SNDR; FOM; voltage references; bandgap; clock circuitry; subADC voltage reference}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI}},
  url          = {{http://dx.doi.org/10.1109/ESSCIRC.2017.8094555}},
  doi          = {{10.1109/ESSCIRC.2017.8094555}},
  year         = {{2017}},
}