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2017
Mark A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI
Palm, Mattias ; Mastantuono, Daniele ; Strandberg, Roland ; Sundström, Lars and Mattisson, Sven ^LU (2017) 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
2003
Mark Verification of a blind mismatch error equalization method for randomly interleaved ADCs using a 2.5V/12b/30MSs PSAADC
Andersson, Martin ^LU ; Elbornsson, J ; Eklund, J-E ; Alvbrant, J and Fredriksson, H (2003) 29th European Solid-State Circuits Conference p.473-476
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding