Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS
(2006) IEEE 13th International Conference on Electronics, Circuits and Systems (ICECS 2006) p.656-659- Abstract
- The power consumption is becoming a major obstacle in future circuit design. Referring to Moore's law, by adding more functionality in an exponential way, we will also increase the total power consumption in the same pace. VLSI design has traditionally been concerning the dynamic power consumption as the limiting factor in low power system design. Today, when the feature sizes are in the nano-meter scale, the static power consumption is becoming a dominating factor. This paper indicates an arithmetic reduction of the static power consumption down to 20 % by using bit-serial arithmetic instead of bit-parallel.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/602937
- author
- Nilsson, Peter LU
- organization
- publishing date
- 2006
- type
- Contribution to conference
- publication status
- published
- subject
- pages
- 656 - 659
- conference name
- IEEE 13th International Conference on Electronics, Circuits and Systems (ICECS 2006)
- conference location
- Nice, France
- conference dates
- 2006-12-10 - 2006-12-13
- external identifiers
-
- wos:000252489600164
- scopus:47349116297
- language
- English
- LU publication?
- yes
- id
- e5c231fe-4d36-4659-8e72-dea5719a62da (old id 602937)
- alternative location
- http://ieeexplore.ieee.org/iel5/4263277/4263278/04263452.pdf?tp=&isnumber=&arnumber=4263452
- date added to LUP
- 2016-04-04 13:27:04
- date last changed
- 2022-03-23 19:57:13
@misc{e5c231fe-4d36-4659-8e72-dea5719a62da,
abstract = {{The power consumption is becoming a major obstacle in future circuit design. Referring to Moore's law, by adding more functionality in an exponential way, we will also increase the total power consumption in the same pace. VLSI design has traditionally been concerning the dynamic power consumption as the limiting factor in low power system design. Today, when the feature sizes are in the nano-meter scale, the static power consumption is becoming a dominating factor. This paper indicates an arithmetic reduction of the static power consumption down to 20 % by using bit-serial arithmetic instead of bit-parallel.}},
author = {{Nilsson, Peter}},
language = {{eng}},
pages = {{656--659}},
title = {{Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS}},
url = {{http://ieeexplore.ieee.org/iel5/4263277/4263278/04263452.pdf?tp=&isnumber=&arnumber=4263452}},
year = {{2006}},
}